The present invention relates to a process for synchronization of matching circuits of a communication system with several modules, which are connected with each other by serial data lines, including providing a transmitter and a receiver in each module as an interface between the serial data lines and a matching circuit; synchronizing at least one other matching circuit with a synchronizing matching circuit and transmitting the required synchronizing signals over the serial data lines; supplying parallel signals from the synchronizing matching circuit to the transmitter connected thereto and converting those parallel signals into serial signals in that transmitter; feeding the serial signals over the serial data lines to the respective receivers connected with the at least one other matching circuit, converting the serial signals into other parallel signals in those respective receivers and supplying the other parallel signals to the at least one other matching circuit connected with the receivers; and generating an error signal in each receiver on detection of a transmission error.
Interface circuits have been provided for serial transmission of data over light guides or coaxial cables in which the data and additional information (commands) can be fed in parallel to a transmitter and on the receiver side the serial data are converted into parallel signals. When this type of interface circuit is used for transmission of data between different modules of a communication system (communication line), a matching circuit is required between the interface circuit and the respective module, especially a bus required for data transmission inside the module. This type of communication system is, for example, described in German Patent Application P 43 24 201.4.
The data transmission presupposes, among other things, besides a synchronization between the transmitter and receiver a synchronization between the matching circuits of the different modules. If that is not the case, for example, in an initial phase after switching on or after interferences, the interface circuits supply indefinite command signals, which disturb the synchronization of the matching circuits and can lead to an erroneous behavior of the entire communication line.